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products and specifications discussed herein ar e subject to change by micron without notice. 64mb: 4 meg x 16 async/page cellularram 1.0 memory features pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_1.fm - rev. g 10/05 en 1 ?2003 micron technology, inc. all rights reserved. async/page cellularram tm 1.0 memory mt45w4mw16p* *note: not recommended for new designs. for the latest data sheet, refer to micron?s web site: http://www.micron.co m/products/psram/ features ? asynchronous and page mode interface ? random access time: 70ns, 85ns ?v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?3.30v v cc q ? page mode read access sixteen-word page size interpage read access: 70ns, 85ns intrapage read access: 20ns, 25ns ?low power consumption asynchronous read: <25ma intrapage read: <15ma standby: 120a ? standard 100a ? low-power option deep power-down: <10a (typ @ 25) ?low-power features temperature-compensated refresh (tcr) partial-array refresh (par) deep power-down (dpd) mode options designator ?configuration 4 meg x 16 mt45w4mw16p 1 ?package 48-ball vfbga (standard) fa 48-ball vfbga (lead-free) ba 2 ?access time 70ns -70 85ns -85 ?standby power standard none low power l figure 1: ball assignment ? 48-ball vfbga notes:1. not recommended for new designs. 2. contact factory. 3. -30c exceeds the cellularram working group 1.0 specification of -25c. part number example : mt45w4mw16pfa-70lwt options (continued) designator ? operating temperature range wireless (-30c to +85c) wt 3 industrial (-40c to +85c) it 2 a b c d e f g h 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 oe# ub# dq10 dq11 dq12 dq13 a19 a8 a0 a3 a5 a17 a21 a14 a12 a9 a2 ce# dq1 dq3 dq4 dq5 we# a11 zz# dq0 dq2 v cc v ss dq6 dq7 a20 a1 a4 a6 a7 a16 a15 a13 a10
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularramtoc.fm - rev. g 10/05 en 2 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory table of contents table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 part-numbering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 temperature-compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 partial-array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 configuration register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 access using zz# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 software access to the configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 partial-array refresh (cr[2:0]) default = ful l array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 sleep mode (cr[4]) default = par enabled, dpd disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 temperature-compensated refresh (cr[6:5]) default = +85c operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 page mode read operation (cr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 maximum and typical standby currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularramlof.fm - rev. g 10/05 en 3 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory list of figures list of figures figure 1: ball assignment ? 48-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram: 4 meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 6: write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 7: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 8: software access par functionalit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 9: load configuration register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 10: software access load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 11: software access read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 12: configuration register bit mappi ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 13: typical refresh current vs. temperature (i tcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: ac input/output reference waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: power-up initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 17: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 18: deep power-down ? entry/exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 19: single read operation (we# = v ih ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 20: page mode read operation (we# = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 21: write cycle (we#-controlled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 22: write cycle (ce#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 23: write cycle (lb#/ub#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 24: 48-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularramlot.fm - rev. g 10/05 en 4 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory list of tables list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 2: bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 3: 64mb address patterns for par (cr[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 4: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 5: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 6: maximum standby currents for applying par and tcr settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: maximum standby currents for applying par and tcr settings ? low-power (l) . . . . . . . . . . . . . .19 table 8: deep power-down specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 9: capacitance specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 10: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 11: read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 12: write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 13: load configuration register timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 14: deep power-down timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 15: power-up initialization timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 16: load configuration register timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 17: deep power-down timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 18: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 19: page mode read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 20: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 21: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 22: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 5 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory general description general description micron ? cellularram? products are high-speed, cmos psram memories developed for low-power, portable applications. the mt45w4mw16pfa is a 64mb dram core device organized as 4 meg x 16 bits. this device includes the industry-standard, asyn- chronous memory interface found on other low-power sram or pseudo sram offerings. operating voltages have been reduced in an effort to minimize power consumption. the core voltage has been reduced to a 1.80v oper ating level. to maintain compatibility with different memory bus interfaces, cellularram devices are available with i/o voltages of 3.0v, 2.5v, or 1.8v. a user-accessible configuration register (cr) defines how the cellularram device per- forms on-chip refresh and whether page mode read accesses are permitted. this register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. to operate seamlessly on an asynchronous memory bus, cellularram products incor- porate a transparent self refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. special attention has been focused on curren t consumption during self refresh. cellular- ram products include three system-accessible mechanisms used to minimize refresh current. temperature-compensated refresh (tcr) is used to adjust the refresh rate according to the case temperature. the refresh rate can be decreased at lower tempera- tures to minimize current consumption during standby. setting sleep enable (zz#) to low enables one of two low-power modes: pa rtial-array refresh (par) or deep power- down (dpd). par limits refresh to only that part of the dram array that contains essen- tial data. dpd halts refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the cr. figure 2: functional block diagram: 4 meg x 16 note: functional block di agrams illustrate simplified device operation. see truth table, ball descriptions, and timing diagrams for detailed information. a[21:0] input/ output mux and buffers control logic 4,096k x 16 dram memory array dq[7:0] dq[15:8] address decode logic lb# ub# ce# w e# oe# zz# configuration register (cr)
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 6 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory general description notes: 1. when lb# and ub# are in select mode (low ), dq[15:0] are affected . when lb# only is in select mode, only dq[7:0] are affected. when ub# only is in the select mode, dq[15:8] are affected. 2. when the device is in standby mode, contro l inputs (we#, oe#), address inputs, and data inputs/outputs are internally isolat ed from any external influence. 3. when we# is invoked, the oe# in put is internally di sabled and has no effect on the i/os. 4. the device will consume active power in this mode whenever addresses are changed. 5. v in = v cc q or 0v; all device balls must be static (unswitched) in order to achieve minimum standby current. 6. dpd is enabled when configuration register bit cr[4] is ?0?; otherwise, par is enabled. table 1: vfbga ball descriptions vfbga ball assignment symbol type description e3, h6, g2, h1, d3, e4, f4, f3, g4, g3, h5, h4, h3, h2, d4, c4, c3, b4, b3, a5, a4, a3 a[21:0] input address inputs: inputs for the address acce ssed during read or write operations. the address lines are also used to define the value to be lo aded into the cr. a6 zz# input sleep enable: when zz# is low, the cr ca n be loaded or the device can enter one of two low-power modes (dpd or par). b5 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. a2 oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: enables write operations when low. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] g1, f1, f2, e2, d2, c2, c1, b1, g6, f6, f5, e5, d5, c6, c5, b6 dq[15:0] input/ output data inputs/outputs. d6 v cc supply device power supply: (1.70v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.70v?3.30v) powe r supply for inpu t/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. table 2: bus operations mode power ce# we# oe# lb#/ub# zz# dq[15:0] 1 notes standby standby h x x x h high-z 2, 5 read active l h l l h data-out 1, 4 write active l l x l h data-in 1, 3, 4 no operation idle l x x x h x 4, 5 par partial-array refresh h x x x l high-z 6 dpd deep power-down h x x x l high-z 6 load configuration register active l l x x l high-z
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 7 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory part-numbering information part-numbering information micron cellularram devices ar e available in several differe nt configurations and densi- ties (see figure 3). figure 3: part number chart note: -30c exceeds the cellularram work ing group 1.0 specification of -25c. valid part number combinations after building the part number from the part numbering chart, please go to the micron part marking decoder web site at http://www.micron.com/partsearch to verify that the part number is offered and valid. if the device required is not on this list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of the device. instead, an abbreviated de vice mark comprised of a five-digit alphanu- meric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at http://www.micron.com/partsearch . to view the location of the abbre- viated mark on the device, please refer to customer service note, csn-11, ?product mark/label,? at http://www.micron.com/csn . mt 45 w 4m w 16 p fa -70 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.70v?1.95v address locations m = megabits operating voltage w = 1.70v?3.30v bus configuration 16 = x16 read/write operation mode p = asynchronous/page package codes fa = vfbga (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball ba = lead-free vfbga (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball (contact factory) production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = -30c to +85c (see note 1) it = -40 to +85c (contact factory) standby power options blank = standard l = low power access/cycle time 70 = 70ns 85 = 85ns
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 8 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory functional description functional description in general, the mt45w4mw16pfa device is a high-density alternative to sram and pseudo sram products, popular in lo w-power, portable applications. the mt45w4mw16pfa contains a 67,108,864-bit dram core organized as 4,194,304 addresses by 16 bits. this device implemen ts the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. page mode accesses are also included as a bandwidth-enhancing extension to the asynchro- nous read protocol. power-up initialization cellularram products include an on-chip volt age sensor that is used to launch the power-up initialization process. initialization will load the cr with its default settings. v cc and v cc q must be applied simultaneously, and when they reach a stable level above 1.70v, the device will require 150s to comp lete its self-initialization process (see figure 4). during the initialization period, ce # should remain high. when initialization is complete, the device is ready for normal operation. at power-up, the cr is set to 0070h. figure 4: power-up initialization timing bus operating modes the mt45w4mw16pfa cellularram product inco rporates the industry-standard, asyn- chronous interface found on other low-power sram or pseudo sram offerings. this bus interface supports asynchronous read and write operations as well as the band- width-enhancing page mode read operation. th e specific interface that is supported is defined by the value loaded into the cr. asynchronous mode cellularram products power up in the asyn chronous operating mode. this mode uses the industry-standard sram control interf ace (ce#, oe#, we#, lb#/ub#). read opera- tions (figure 5) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 6) occur when ce#, we#, and lb#/ub# are driven low. during write operations, the level of oe# is a ?don't care?; we# will override oe#. the data to be written will be latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). we# low time must be limited to t cem. vcc vccq device initialization vcc = 1.7v device ready for normal operation t pu > 150s
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 9 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory bus operating modes figure 5: read operation figure 6: write operation address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time address < t cem
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 10 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory bus operating modes page mode read operation page mode is a performance-enhancing exte nsion to the legacy asynchronous read operation. in page-mode-capable products, an initial asynchronous read access is per- formed, then adjacent addresses can be quickly read by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellular- ram page. any changes in addresses a[4] or higher will initiate a new t aa access. figure 7 shows the timing diagram for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. wr ite operations do no t include comparable page mode functionality. the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem. figure 7: page read operation lb#/ub# operation the lower byte (lb#) enable and upper byte (ub#) enable signal s allow for byte-wide data transfers. during read operations, enabled bytes are driven onto the dq. the dq associated with a disabled byte are put into a high-z state during a read operation. during write operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. during a write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (hig h) during an operation, the device will disable the data bus from receiving or transm itting data. although the device will seem to be deselected, the device remains in an active mode as long as ce# remains low. data ce# don?t care oe# we# lb#/ub# address add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa t apa t apa d[0] < t cem
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 11 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory low-power operation low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to per- form the dram refresh operation on the full array. standby operation occurs when ce# and zz# are high. the device will enter a reduced power stat e during read and write operations where the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature-compensated refresh temperature-compensated refresh is used to adjust the refresh rate depending on the device operating temperature. dram technology requires more frequent refresh operations to maintain data integrity as temp eratures increase. more frequent refresh is required due to the increased leakage of the dram?s capacitive storage elements as tem- peratures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. for ex ample, if the case temperature is +50c, the system can minimize self refresh current consumption by selecting the +70c set- ting. the +15c and +45c settings would result in inadequate refreshing and cause data corruption. partial-array refresh partial-array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. the refresh options are full array, one-half array, one-quarter array, one-eighth ar ray, or none of the array. data stored in addresses not receiving refresh will become corrupted. the mapping of these partitions can start at either the beginning or the end of the address map (see table 3 on page 15). read and write operations are ignored during par operation. the device only enters par mode if the sleep bit in the cr has been set high (cr[4] = 1). par can be initiated by bringing zz# to the low state for longer than 10s. returning zz# to high will cause an exit from par an d the entire array will be immediately avail- able for read and write operations. alternatively, par can be initiated using the cr software access sequence (see software access to the configuration register on pa ge 13). par is enabled immediately upon set- ting cr[4] to ?1? using this method. however, using software access to write to the cr alters the function of zz# so that zz# low no longer initiates par, although zz# contin- ues to enable writes to the cr. this functi onal change persists until the next time the device is powered up. (see figure 8.) the device can only enter dpd if the sleep bi t in the cr has been set low (cr[4] = 0). dpd is initiated by bringing zz# to the low state for longer than 10s. returning zz# to high will cause the device to exit dpd and begin a 150s initialization process. during this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. driving zz# low will place the device in the par mode if the sleep bit in the cr has been set high (cr[4] = 1). the device should not be put into dpd using cr software access.
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 12 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory low-power operation figure 8: software access par functionality deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used when the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is entered. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. read and write operations are ignored during dpd operation. no yes power-up to enable par, bring zz# low for 10s. change to zz# functionality. par permanently enabled, independent of zz# level. software load executed?
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 13 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory configuration register operation configuration register operation the configuration register (cr) defines how the cellularram device performs its trans- parent self refresh. altering the refresh parameters can dramatically reduce current con- sumption during standby mode. page mode co ntrol is also embedded into the cr. this register can be updated anytime while the device is operating in a standby state. figure 12 on page 15 describes the control bits used in the cr. at power up, the cr is set to 0070h. access using zz# the cr can be loaded using a write oper ation immediately afte r zz# makes a high- to-low transition (figure 9). the values plac ed on addresses a[21:0] are latched into the cr on the rising edge of ce# or we#, whiche ver occurs first. lb#/ub# are ?don?t care.? access using zz# is write only. figure 9: load configuration register operation software access to the configuration register the contents of the cr can either be read or modified using a software sequence. the nature of this access mechanism may eliminate the need for zz# ball. if the software mechanism is used, zz# can simply be tied to v cc q. the port line typi- cally used for zz# control purposes will no longer be required. however, zz# should not be tied to v cc q if the system will use dpd; dpd cannot be enabled or disabled using the software access sequence. the cr is loaded using a four-step sequence consisting of two read operations followed by two write operations (see figure 10). the read sequence is virtually identical except that an asynchronous read is performed du ring the fourth operation (see figure 11). note that a third read cycle of the highest address cancels the sequence until a different address is read. the address used during all read and write operations is the highest address of the cellularram device being accessed (3fffffh for 64mb); the content at this address is changed by using this sequence (note that th is is a deviation from the cellularram spec- ification). the data bus is used to transfer data into or out of bits 15?0 of the cr. writing to the cr using the software sequen ce modifies the function of zz#. once the software sequence loads the cr, the zz# le vel no longer enables par operation. par operation will be updated whenever the soft ware sequence loads a new value into the cr. this zz# functionality will continue unti l the next time the device is powered up. the operation of zz# is not affected if the software sequence is only used to read the contents of the cr. the use of the software sequence does not affect the ability to per- form the standard (zz#-controlle d) method of loading the cr. address valid ce# zz# we# t < 500ns address
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 14 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory configuration register operation figure 10: software access load configuration register note: the write on the third cy cle must be ce #-controlled. figure 11: software access read configuration register notes: 1. the write on the third cycle must be ce#-controlled. 2. ce# must be high for 150ns before performing the cycle that reads the configuration reg- ister. address (max) address (max) address (max) xxxxh xxxxh cr value in a ddress ce# oe# we# lb#/ub# data don't care read read write 1 write address (max) 0000h address (max) address (max) address (max) xxxxh xxxxh cr value out a ddress ce# oe# we# lb#/ub# data don't care read read write 1 read note 2 address (max) 0000h
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 15 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory configuration register operation figure 12: configuration register bit mapping partial-array refresh (cr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this fea- ture allows the system to reduce current by on ly refreshing that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quar- ter array, one-eighth array, or none of th e array. the mapping of these partitions can start at either the beginning or the end of the address map (see table 3). sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit determines which low-power mode is to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd operation is enabled. par can also be enabled directly by writing to the cr using the software access sequence. note that this then disables zz# in itiation of par. dpd cannot be enabled or disabled using the software access sequence; this should only be done using zz# to access the cr. table 3: 64mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h?3 fffffh 4 meg x 16 64mb 0 0 1 one-half of die 00000 0h?1fffffh 2 meg x 16 32mb 0 1 0 one-quarter of die 00 0000h?0fffffh 1 meg x 16 16mb 0 1 1 one-eighth of die 00 0000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 20000 0h?3fffffh 2 meg x 16 32mb 1 1 0 one-quarter of die 30 0000h?3fffffh 1 meg x 16 16mb 1 1 1 one-eighth of die 38 0000h?3fffffh 512k x 16 8mb par a4 a3 a2 a1 a0 configuration register address bus 4 1 2 3 0 reserved 6 5 a5 0 1 sleep mode dpd enabled par enabled (default) cr[4] tcr cr[6] cr[5] 11 1 1 00 0 0 maximum case temp. +85?c (default) +70?c +45?c +15?c a6 21? 8 reserved a[21:8] cr[1] cr[0] par refresh coverage full array (default) bottom 1/2 array bottom 1/4 array bottom 1/8 array none of array top 1/2 array top 1/4 array top 1/8 array 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 cr[2] sleep must be set to "0" all must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enabled cr[7]
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 16 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory configuration register operation dpd operation disables all refresh-related activity. this mode will be used when the sys- tem does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operation can resume. dpd should not be enabled using cr software access. temperature-compensated refresh (c r[6:5]) default = +85c operation the tcr bits allow for adequate refresh at fo ur different temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. if the case temperature is +50c, the system can minimize self refresh cu rrent consumption by selectin g the +70c setting. the +15c and +45c settings would result in inadequa te refreshing and cause data corruption. page mode read operatio n (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled. in the power-up default state, page mode is disabled.
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 17 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics electrical characteristics stresses greater than those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. -30c exceeds the cellularram wo rking group 1.0 specification of -25c. table 4: absolute maximum ratings parameter rating voltage to any ball except v cc , v cc q relative to v ss -0.50v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss -0.20v to 2.45v voltage on v cc q supply relative to v ss -0.20v to 4.0v storage temperature -55c to +150c operating temperature (case) wireless (see note 1) industrial -30c to +85c -40c to +85c soldering temperature and time 10s (solder ball only) +260c
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 18 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics notes: 1. -30c exceeds the cellularram wo rking group 1.0 specification of -25c. 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. v ih (min) value is not aligned with cellularram working group 1.0 specification of v cc q - 0.4v. 4. input signals ma y undershoot to v ss - 1.0v for periods less than 2ns during transitions 5. this parameter is specified with the outputs di sabled to avoid external loading effects. the user must add the current required to drive out put capacitance expected in the actual sys- tem. 6. i sb (max) values measured with par set to fu ll array and tcr set to +85c. in order to achieve low standby current, al l inputs must be driven to v cc q or v ss . i sb may be slightly higher for up to 500ms after power- up or when entering standby mode. table 5: electrical characteristics and operating conditions wireless temperature 1 (-30oc t c +85 oc), industrial temperature (-40oc < t c < +85oc). description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q 1.70 3.30 v input high voltage v ih 1.4 v cc q + 0.2 v 2, 3 input low voltage v il -0.2 +0.4 v 4 output high voltage i oh = -0.2ma v oh 0.80 v cc qv output low voltage i ol = 0.2ma v ol 0.20 v cc qv input leakage current v in = 0 to v cc qi li 1 a output leakage current oe# = v ih or chip disabled i lo 1 a operating current asynchronous random read/write v in = v cc q or 0v chip enabled, i out = 0 i cc 1 -70 25 ma 5 -85 20 asynchronous page read i cc 1p -70 15 ma 5 -85 12 standby current v in = v cc q or 0v ce# = v cc q i sb standard 120 a6 low-power (l) 100
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 19 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics maximum and typical standby currents the following tables and figures refer to the maximum and typical standby currents for the mt45w4mw16pfa device. the typical values shown in figure 13 are measured with the appropriate par and tcr settings. the maximum values shown in table 6 and table 7 are measured with the relevant tcr bits set in the configuration register. notes: 1. for rcr[6:5] = 00b (default), refer to figure 13, typical refresh current vs. temperature (i tcr ), on page 20 for typical values. 2. in order to achieve low standby curr ent, all inputs must be driven to v cc q or v ss . i sb may be slightly higher for up to 500ms after power-up or when entering standby mode. 3. tcr values for 85c are 100 percent tested. tcr values for 15c, 45c, and 70c are sam- pled only. notes: 1. for rcr[6:5] = 00b (default), refer to figure 13, typical refresh current vs. temperature (i tcr ), on page 20 for typical values. 2. in order to achieve low standby curr ent, all inputs must be driven to v cc q or v ss . i sb may be slightly higher for up to 500ms after power-up or when entering standby mode. 3. tcr values for 85c are 100 percent tested. tcr values for 15c, 45c, and 70c are sam- pled only. table 6: maximum standby currents for applying par and tcr settings par tcr +15c (rcr[6:5] = 10b) +45c (rcr[6:5] = 01b) +70c (rcr[6:5] = 00b) +85c (rcr[6:5] = 11b) full array 70 85 105 120 1/2 array 65 80 100 115 1/4 array 60 75 95 110 1/8 array 57 70 90 105 0 array 50 55 60 70 table 7: maximum standby currents for applying par and tcr settings ? low-power (l) par tcr +15c (rcr[6:5] = 10b) +45c (rcr[6:5] = 01b) +70c (rcr[6:5] = 00b) +85c (rcr[6:5] = 11b) full array 60 70 85 100 1/2 array 57 65 80 95 1/4 array 54 61 75 90 1/8 array 52 58 70 85 0 array 50 55 60 70
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 20 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics figure 13: typical refresh current vs. temperature (i tcr ) note: typical i sb currents for each par setting wi th the appropriate tcr selected. table 8: deep power-down sp ecifications and conditions description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c zz# = 0v cr[4] = 0 i zz 10 a 0 10 20 30 40 50 6 0 70 -30 -20 -10 0 10 20 30 40 50 6 0708090 temperature ( c ) i s b (a) par = full array par = 1/2 of array par = 1/4 of array par = 1/8 of array par = none of array
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 21 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics notes: 1. these parameters are verified in device characterization and are not 100 percent tested. figure 14: ac input/output reference waveform notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss q for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc /2. due to the possibility of a difference between v cc and v cc q, the input test point may not be shown to scale. 3. output timing ends at v cc q/2. figure 15: output load circuit table 9: capacitance spec ifications and conditions description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6 pf 1 input/output capacitance (dq) c io 2.5 6 pf 1 table 10: output load circuit v cc q r1/r2 1.8v 2.7k 2.5v 3.7k 3.0v 4.5k output test points input 1 v cc q v ss q v cc q/2 3 v cc /2 2 dut vccq r1 r2 30pf test point
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 22 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics notes: 1. high-z to low-z timings are tested with the circuit show n in figure 15 on page 21. the low-z timings measure a 100mv tra nsition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 15 on page 21. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 3. page-mode enabled only. table 11: read cycle timing requirements parameter symbol -70 -85 units notes min max min max address access time t aa 70 85 ns page access time t apa 20 25 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to high-z output t bhz 88ns2 lb#/ub# enable to low-z output t blz 10 10 ns 1 maximum ce# pulse width t cem 88s3 chip select access time t co 70 85 ns chip disable to high-z output t hz 88ns2 chip enable to low-z output t lz 10 10 ns 1 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to high-z output t ohz 88ns2 output enable to low-z output t olz 55ns1 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 23 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics notes: 1. high-z to low-z timings are tested with the circuit show n in figure 15 on page 21. the low-z timings measure a 100mv tra nsition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 15 on page 21. the high-z timings measure a 100mv transition fr om either v oh or v ol toward v cc q/2. 3. we# low time must be limited to t cem (8s). table 12: write cycle timing requirements parameter symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns byte select to end of write t bw 70 85 ns ce# high time during write t cph 55ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 25 ns chip enable to low-z output t lz 10 10 ns 1 end write to low-z output t ow 55ns1 write cycle time t wc 70 85 ns write to high-z output t whz 88ns2 write pulse width t wp 46 50 ns 3 write pulse width high t wph 10 10 ns write recovery time t wr 00ns
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 24 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory electrical characteristics table 13: load configuration register timing requirements description symbol -70 -85 units min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns chip deselect to zz# low t cdzz 55ns chip enable to end of write t cw 70 85 ns write cycle time t wc 70 85 ns write pulse width t wp 40 40 ns write recovery time t wr 00ns zz# low to we# low t zzwe 10 500 10 500 ns table 14: deep power-down timing requirements description symbol -70 -85 units min max min max chip deselect to zz# low t cdzz 55ns deep power-down recovery t r 150 150 s minimum zz# pulse width t zzmin 10 10 s
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 25 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams timing diagrams figure 16: power-up initialization period figure 17: load configuration register table 15: power-up initialization timing requirements parameter symbol -70 -85 units min max min max power-up initialization period t pu 150 150 s table 16: load configuration register timing requirements symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t wc 70 85 ns t aw 70 85 ns t wp 40 40 ns t cdzz 55ns t wr 00ns t cw 70 85 ns t zzwe 1050010500ns device ready fo r normal operation vcc, vccq = 1.7v t pu vcc (min) address zz# t wc t aw t wr t as ce# lb#/ub# t zzwe don?t care we# t wp t cdzz opcode t cw oe#
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 26 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 18: deep power-down ? entry/exit table 17: deep power-down timing parameters symbol -70 -85 units min max min max t cdzz 55ns t r 150 150 s t zz (min) 10 10 s zz# ce# t zz (min) don?t care t cdzz t r device ready for normal operation
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 27 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 19: single read operation (we# = v ih ) table 18: read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t co 70 85 ns t rc 70 85 ns t hz 88ns address oe# t rc t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid t ohz t ba t bhz t hz t blz t co t oe address valid
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 28 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 20: page mode read operation (we# = v ih ) table 19: page mode read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t apa 20 25 ns t oe 20 20 ns t ba 70 85 ns t oh 55ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t cem 88s t pc 20 25 ns t co 70 85 ns t rc 70 85 ns t hz 88ns address a[21:4] oe# t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid data valid data valid data valid t ohz t ba t bhz t hz t cem t blz t co address a[3:0] t rc t oh t pc address valid t apa t oe
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 29 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 21: write cycle (we#-controlled) table 20: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t ow 55ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88ns t cw 70 85 ns t wp 46 50 ns t dh 00ns t wph 10 10 ns t dw 23 25 ns t wr 00ns address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t ow t dh t dw t as t wp t wph don?t care high-z data-out data valid t cw oe# address valid
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 30 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 22: write cycle (ce#-controlled) table 21: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cph 55ns t whz 88ns t cw 70 85 ns t wp 46 50 ns t dh 00ns t wr 00ns address we# t wc t aw t cw t wr t cph data-in ce# lb#/ub# t bw t whz t lz t as t dh t dw t wp don?t care high-z data-out data valid oe#
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 31 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams figure 23: write cycle (lb#/ub#-controlled) table 22: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cw 70 85 ns t whz 88ns t dh 00ns t wr 00ns address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t dh t as t dw t lz don?t care data-out data valid t cw oe# high-z
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. cellularram is a tra demark of micron technology, inc., inside the u.s. and a tradem ark of infineon technologies outside the u.s. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 64mb: 4 meg x 16 async/page cellularram 1.0 memory timing diagrams pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 32 ?2003 micron technology, inc. all rights reserved. figure 24: 48-ball vfbga notes: 1. all dimensions in millimete rs, max/min, or typical where noted. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. ball a1 id 1.00 max 4.00 0.05 3.00 0.05 1.875 6 .00 0.10 c l c l s older ball material: 6 2 % s n, 3 6% p b , 2 % a g or 9 6 .5 % s n, 3 % a g , 0.5 % c u s older ball pad: ?0.30 s older ma s k defined mold c ompound: epoxy novola c s ub s trate material: pla s ti c laminate 0.75 typ 0.75 typ 8.00 0.10 5.25 2. 6 25 0.05 ball a1 ball a1 id 3.75 0.70 0.05 s eatin g plane 0.10 c c ball a 6 s older ball diameter refer s to po s t reflow c ondition. the pre-reflow diameter i s ?0.35. 48x ?0.37
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 33 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory revision history revision history ? rev g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/05 ? added new p25a-specific note to the cover page. ? rev f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04/05 ? removed 60ns support. ? corrected typographic errors. ? rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/04 ? removed all references to 32mb density. ? added table 6, maximum standby currents for applying par and tcr settings, on page 19 ? added table 7, maximum standby currents for applying par and tcr settings ? low-power (l), on page 19 ? added figure 13, typical refresh current vs. temperature (i tcr ), on page 20 ? added ?maximum and typical standby currents? on page 19 ? rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/04 ? we# low limited to t cem for writes. ? last address changed by software access sequence. ? noted software access third cycle must be ce#-controlled write. ?change t ceh to t cph. ? clarified tcr temperatures and setting in table 6. ? changed vccq option w to 1.70v?3.30v. ? changed wireless temperature range to -30c. ? noted input high voltage not aligned wi th the working group specification of v cc q - 0.4. ? noted wireless temp (min) exceeds the working group spec. ? rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 05/04 ? clarified ce# low time limited by re fresh?must not stay low longer than t cem. ?changed t cem max to 8. ? clarified address a[4] and higher in page mode. ?clarified i cc and updated symbols. ? changed par options to full, one-half, one-quarter, one-eighth, or none. ? deleted appendix a (extended timings and all references). ?added c in and c io min values. ? replaced abbreviated component mark s table with part numbering chart. ? added measurement time clarification to i sb and i par notes ? corrected package nomenclature to vfbga. ? we# low limited to t cem for writes. ? last address changed by software access sequence. ? noted software access third cycle must be ce#-controlled write. ?change t ceh to t cph. ? rev. b, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 ? prohibited dpd via software access. ? updated appendix regarding async page mode. ?added t wph, t cem, and t cw to tables and figures where not already appropriately represented. ? added ?access using zz#? section. ? added software access section.
pdf: 09005aef80be1ee8/source: 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_2.fm - rev. g 10/05 en 34 ?2003 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 async/page cellularram 1.0 memory revision history ? added standard and low-power data in tables 8 & 9. ? v, it, and -60 now ?contact factory. ? rev. a, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 07/03 ? input/output leakage to 1a. ? added industrial temperature. ? changed standby power to 90a and 100a. ? changed input high voltage max to vccq + 0.2.

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